An SDRAM-Aware Router for Networks-on-Chip
نویسندگان
چکیده
منابع مشابه
Cost-aware Topology Customization of Mesh-based Networks-on-Chip
Nowadays, the growing demand for supporting multiple applications causes to use multiple IPs onto the chip. In fact, finding truly scalable communication architecture will be a critical concern. To this end, the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication challenges within the silicon-based electronics. Many of today’s NoC architectures are based...
متن کاملAn Analytical Router Model for Networks-On-Chip
The proposed system is based on analytical model of Router and queueing theory. This approach not only provides aggregate performance metrics such as average latency and throughput, but also feedback about the network characteristics such as buffer utilization, average latency per router and per flow at a finelevel of granularity. The proposed analytical model can predict the average packet lat...
متن کاملfive-port optical router design based on mach–zehnder switches for photonic networks-on-chip
we design and simulate a five-port optical router, which is composed of twenty mach-zehnder-based switching elements and twelve waveguide crossings for use in integrated photonic interconnection networks. we simulated and analyzed the operation of the proposed optical router from the aspects of insertion loss, power budget, q-factor and the minimum bit error ratio by use of optisystem simulator...
متن کاملDesign of a Switching Node (Router) for On-Chip Networks
Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional interconnects, such as on-chip networks (OCN), must be used. Our OCN is capable of providing a data transfer throughput of 19.2 Gbps/link. The key element of our OCN is the switching node. We present a prototype desig...
متن کاملAsynchronous Router Design for Scalable GALS Networks on Chip
The aggressive scaling of multi-core designs in embedded and desktop domains has lead to the incorporation of scalable networks on chip (NoC) as the physical communication medium. There is a significant demand for low-latency and high-throughput communication via these networks. Heterogeneous designs in embedded applications have additional communication demands including lower power consumed b...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 2010
ISSN: 0278-0070,1937-4151
DOI: 10.1109/tcad.2010.2061251